In a typical thin film transistor (TFT) liquid crystal display (LCD), a plurality of pixels are formed in an active region of a substrate. Each pixel typically includes a pixel electrode connected to a thin film transistor. Gate lines and data lines typically are connected to gate electrodes and source electrodes, respectively, of the thin film transistors, and a pad may be connected to each of the gate lines and the data lines for receiving a signal for driving the gate electrodes and source electrodes. These pads typically are formed in an out lead bonding (OLB) pad region on the substrate, at the periphery of the active region.
A TFT substrate may be exposed to electrostatic discharge during processing and handling. This may cause destruction of the TFTs or deterioration of their electrical characteristics. To prevent these problems, wiring patterns on the substrate may be connected to a shorting bar or a conductive ring, either directly or indirectly through resistors, diodes or TFTs to allow the wiring to be held at a common potential.
As shown, a plurality of gate lines 1 and a plurality of data lines 2 are formed on a substrate consisting of an active region A and a pad region B. A plurality of TFTs and a plurality of pixel electrodes are formed in the active region A. A plurality of gate pads 3 and data pads 4, respectively connected to the gate lines 1 and the data lines 2, are formed in a pad region B. Connecting members such as the shorting bars 5 and 6 illustrated in FIG. 1 and the conductive rings 80 and 8 illustrated in FIGS. 2 and 3 may be formed in the pad region B of the substrate.
As shown in FIG. 1, the connecting member may include a gate shorting bar 6 and a data shorting bar 6 which are connected to gate pads 3 and the data pads 4, respectively. The gate shorting bar 5 and the data shorting bar 6 are connected to each other through a resistor 7. As shown in FIG. 2, a conductive ring 80 may be connected to the gate pads 3 and the data pads 4 through transmission gates 9. A first gate terminal and a common drain terminal of a transmission gate 9 are connected to the ring 80, and a second gate terminal and a common source terminal of the transmission gate 9 are connected to a gate pad 3 or a data pad 4.
As shown in FIG. 3, a conductive ring 8 may be formed which crosses the gate lines 1 and the data lines 2 and which is insulated from the gate lines 1 and the data lines 2. First and second thin film transistors I and II connect the ring 8 and the gate lines 1 and the data lines 2. A gate and a drain of the first thin film transistor I are connected to the ring 8, while the source of the first thin film transistor I is connected to the gate line 1 or the data line 2. A gate and a source of the second thin film transistor II are connected to the gate line 1 or the data line 2, while the drain at the second thin film transistor II is connected to the ring 8.
For the conventional electrostatic discharge protection circuit of FIG. 1, the shorting bars typically are disconnected from the gate lines and the data lines in order to test for wiring defects. Unfortunately, the substrate may be further exposed to electrostatic charges subsequent to testing for defects, thus exposing the devices on the substrate to potential damage. For the configurations of FIGS. 2 and 3, electrostatic charges may be generated near a pad of a certain gate line or data line, causing transmission gates and the TFTs near the pad to be destroyed and disconnecting the gate line or the data line from the ring. Charge currents may then flow into the active region through the wiring and may destroy TFTs or other elements.